Hardware architecture and implementation of low power layered multi-level LDPC decoder
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United States of America Patent
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May 19, 2015
Grant Date -
May 1, 2014
app pub date -
Oct 30, 2012
filing date -
Oct 30, 2012
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Abstract
A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.
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