Load pair disjoint facility and instruction therefor

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United States of America Patent

PATENT NO 9052889
APP PUB NO 20130117546A1
SERIAL NO

13726746

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Abstract

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A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jacobi, Christian Poughkeepsie, US 381 3569
Mitran, Marcel Markham, US 96 1242
Slegel, Timothy J Staatsburg, US 400 5854
Webb, Charles F Wappingers Falls, US 64 1324

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