Corrosion/etching protection in integration circuit fabrications

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United States of America Patent

PATENT NO 9054109
APP PUB NO 20130320544A1
SERIAL NO

13482352

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Abstract

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A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Wei Albany, US 535 4306
Nguyen, Son Schenectady, US 112 4058
Paruchuri, Vamsi Clifton Park, US 26 299
Vo, Tuan A Albany, US 36 650

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