Charge breakdown avoidance for MIM elements in SOI base technology and method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9059131
APP PUB NO 20140015093A1
SERIAL NO

14030414

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Abstract

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A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Clark,, Jr William F Essex Junction, US 52 256
Luce, Stephen E Underhill, US 56 1407

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