Wafer leveled chip packaging structure and method thereof
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United States of America Patent
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Jun 16, 2015
Grant Date -
Aug 7, 2014
app pub date -
Nov 18, 2013
filing date -
Jul 23, 2004
priority date (Note) -
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Abstract
A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
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