Strained channel for depleted channel semiconductor devices
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United States of America Patent
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Jun 16, 2015
Grant Date -
Aug 8, 2013
app pub date -
Sep 13, 2012
filing date -
Feb 2, 2012
priority date (Note) -
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Abstract
A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.
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