Back-end transistors with highly doped low-temperature contacts
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United States of America Patent
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Jun 16, 2015
Grant Date -
May 1, 2014
app pub date -
Oct 31, 2012
filing date -
Oct 31, 2012
priority date (Note) -
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Abstract
A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.
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