Method and apparatus for fabricating a memory device with a dielectric etch stop layer
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United States of America Patent
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Jun 23, 2015
Grant Date -
Nov 16, 2006
app pub date -
Jul 24, 2006
filing date -
Apr 27, 2004
priority date (Note) -
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Abstract
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.
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