Frequency-agile clock multiplier
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United States of America Patent
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Jun 23, 2015
Issued Date -
N/A
app pub date -
Oct 17, 2014
filing date -
Jul 1, 2011
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Abstract
A clock generating circuit is operated in a closed-loop state to generate an output clock signal that is frequency-locked with respect to an oscillatory input signal. Upon detecting a frequency transition in the input signal, the clock generating circuit is switched from the closed-loop operating state to an open-loop operating state to enable the output clock signal to oscillate at a free-running frequency. A ratio between input signal frequency and the free-running frequency of the output clock signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output clock signal with respect to input signal.
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