PARALLEL-SERIAL CONVERTER CIRCUIT
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United States of America Patent
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Jun 30, 2015
Grant Date -
Jul 16, 2015
app pub date -
Sep 9, 2014
filing date -
Jan 16, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.
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