Successive approximation analog-to-digital converter with linearity error correction
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United States of America Patent
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Jun 30, 2015
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app pub date -
Aug 12, 2014
filing date -
Aug 12, 2014
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Abstract
A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.
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