Semiconductor device structures including strained transistor channels

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United States of America Patent

PATENT NO 9076867
APP PUB NO 20140167186A1
SERIAL NO

14188186

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Abstract

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The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhattacharyya, Arup Essex Jct., US 228 9476
Farrar, Paul A Okatie, US 236 4301
Forbes, Leonard Corvallis, US 1219 61532

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