Clock regeneration circuit, light receiving circuit, photocoupler, and frequency synthesizer
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United States of America Patent
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Jul 7, 2015
Grant Date -
Jun 5, 2014
app pub date -
Nov 27, 2013
filing date -
Nov 30, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A clock regeneration circuit includes: a signal input terminal; a D flip-flop circuit; a reset signal generation circuit; a delay circuit; a comparator; a first capacitor; and a feed back circuit. The signal input terminal is inputted with a pulse width modulation signal. The D flip-flop circuit includes a clock terminal, an output terminal, and a reset terminal. The reset signal generation circuit is configured to input a reset signal generated in synchronization with the pulse width modulation signal to the reset terminal at a first time. The delay circuit is configured to delay the pulse width modulation signal. The feedback circuit includes a current source having a control terminal. The feedback circuit is configured to change one of charge rise time and discharge fall time in response to the signal of the comparator to control duty cycle of the signal of the comparator.
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