Memory controller, storage device and memory control method
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United States of America Patent
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Jul 7, 2015
Grant Date -
Aug 28, 2014
app pub date -
Jul 25, 2013
filing date -
Feb 27, 2013
priority date (Note) -
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Abstract
According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability.
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