Application memory preservation for dynamic calibration of memory interfaces
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United States of America Patent
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Jul 14, 2015
Grant Date -
May 8, 2014
app pub date -
Jan 10, 2014
filing date -
Jun 6, 2008
priority date (Note) -
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Abstract
A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.
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