Power napping technique for accelerated negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) recovery
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United States of America Patent
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Jul 21, 2015
Grant Date -
Jan 9, 2014
app pub date -
Jul 9, 2012
filing date -
Jul 9, 2012
priority date (Note) -
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Abstract
A logic circuit is operated in a normal mode, with a supply voltage coupled to a supply rail of the logic circuit, and with a ground rail of the logic circuit grounded; It is determined that at least a portion of the logic circuit has experienced degradation due to bias temperature instability. Responsive to the determining, the logic circuit is operated in a power napping mode, with the supply voltage coupled to the ground rail of the circuit, with the supply rail of the circuit grounded, and with primary inputs of the circuit toggled between logical zero and logical one at low frequency. A logic circuit and corresponding design structures are also provided.
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