Flash memory device reducing layout area
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United States of America Patent
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Jul 21, 2015
Issued Date -
N/A
app pub date -
Jan 14, 2014
filing date -
Feb 18, 2013
priority date (Note) -
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Abstract
A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.
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