Thin heterostructure channel device
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United States of America Patent
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Jul 21, 2015
Grant Date -
Jun 27, 2013
app pub date -
Dec 23, 2011
filing date -
Dec 23, 2011
priority date (Note) -
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Abstract
A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
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