Semiconductor fabrication method using stop layer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 21, 2015
Grant Date -
Aug 28, 2014
app pub date -
Feb 26, 2013
filing date -
Feb 26, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully