RAM based implementation for scalable, reliable high speed event counters
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United States of America Patent
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Jul 21, 2015
Grant Date -
Jul 4, 2013
app pub date -
Feb 25, 2013
filing date -
Jul 31, 2008
priority date (Note) -
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Abstract
There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.
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