Dynamic memory performance throttling
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United States of America Patent
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Aug 11, 2015
Grant Date -
Jan 9, 2014
app pub date -
Dec 23, 2011
filing date -
Dec 23, 2011
priority date (Note) -
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Abstract
Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misalignment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.
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