eDRAM refresh in a high performance cache architecture
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United States of America Patent
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Aug 11, 2015
Grant Date -
Dec 29, 2011
app pub date -
Jun 24, 2010
filing date -
Jun 24, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.
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