Fault tolerant control line configuration
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United States of America Patent
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Aug 11, 2015
Grant Date -
May 1, 2014
app pub date -
Oct 31, 2012
filing date -
Oct 31, 2012
priority date (Note) -
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Abstract
A fault tolerant control line configuration useful in a variety of solid state memories such as but not limited to a flash memory. In accordance with some embodiments, an apparatus includes a plurality of memory cells, and a fault tolerant control line. The control line has an elongated first conductive path connected to each of the plurality of memory cells. An elongated second conductive path is disposed in a parallel, spaced apart relation to the first conductive path. A plurality of conductive support members are interposed between the first and second conductive paths to support the second conductive path above the first conductive path.
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