Ball grid array and card skew matching optimization
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United States of America Patent
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Aug 11, 2015
Grant Date -
Apr 14, 2011
app pub date -
Dec 17, 2010
filing date -
Jan 9, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
A method, system, and computer storage device simultaneously compare the timing of conductive signal paths in a substrate and a printed circuit board to achieve a predetermined signal timing goal. Specifically, the method automatically calculates a substrate-based length of time it will take a signal to pass within each substrate conductor (within a conductor group) and automatically calculates a board-based length of time it will take a signal to pass within each of board conductors (within the conductor group). The method automatically adds the substrate-based length of time and the board-based length of time for each of the combined substrate-board conductors to produce a combined timing for each of the combined substrate-board conductors. The method automatically compares the combined timing of each the combined substrate-board conductors to determine whether the combined substrate-board conductors pass signals within a predetermined timing variance limit.
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