Method and structure to enhance gate induced strain effect in multigate device
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United States of America Patent
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Aug 11, 2015
Grant Date -
Jul 23, 2015
app pub date -
Jan 23, 2014
filing date -
Jan 23, 2014
priority date (Note) -
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Abstract
A FinFet formed by depositing a thin layer of polycrystalline silicon followed by depositing a stress containing material, including a high Ge percentage silicon germanium film and/or a high stress W film on top of a polycrystalline silicon film. Freeing space between fins allows stressor films to be deposited closer to the transistor channel, improving the proximity of the stress containing material to the transistor channel and enhancing the stress coupling efficiency by defining a ratio between stress level in the stressor film and stress transferred to the channel for a mobility enhancement. The stress level is enhanced by patterning by removing the n-type workfunction metal from the p-FinFET. After stripping off the soft or hard mask, the p-type workfunction metal is deposited in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility.
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