Input/output delay testing for devices utilizing on-chip delay generation
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United States of America Patent
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Aug 18, 2015
Grant Date -
Jul 3, 2014
app pub date -
Dec 27, 2012
filing date -
Dec 27, 2012
priority date (Note) -
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Abstract
I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.
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