Importance

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Abstract

A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.

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First Claim