Reduced resistance finFET device with late spacer self aligned contact

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United States of America Patent

PATENT NO 9112031
APP PUB NO 20150129988A1
SERIAL NO

14075033

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Abstract

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Embodiments include a method of fabricating a reduced resistance finFET device comprising providing a fin in a semiconductor substrate. A dummy gate is formed over a portion of the fin such that the dummy gate does not initiate selective epitaxy. A source/drain region is formed on the fin such that the source/drain region directly contacts the dummy gate. The dummy gate is replaced with a replacement metal gate structure that directly contacts the source/drain region. A portion of the fin that includes a portion of the source/drain region is replaced with a contact material.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Leobandung, Effendi Stormville, US 536 4779

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