DLL circuit and semiconductor device
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United States of America Patent
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Aug 18, 2015
Grant Date -
May 15, 2014
app pub date -
Sep 10, 2013
filing date -
Nov 9, 2012
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor device is provided with first to third circuits. The first circuit generates first information that indicates a corresponding relationship between a period of a reference clock and a delay amount per delay element. The second circuit generates second information that indicates the number of stages of delay elements corresponding to a set phase difference based on the first information. The third circuit generates a delayed clock by delaying the reference clock just a delay amount of stages of the delay elements indicating the second information.
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