Packing in destination register half of each element with saturation from two source packed data registers
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United States of America Patent
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Aug 25, 2015
Grant Date -
May 16, 2013
app pub date -
Dec 29, 2012
filing date -
Dec 2, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
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