Interconnection of semiconductor device with graphene wire
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United States of America Patent
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Aug 25, 2015
Grant Date -
Aug 21, 2014
app pub date -
Aug 13, 2013
filing date -
Feb 15, 2013
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
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