Pipelined data relocation and improved chip architectures
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United States of America Patent
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Sep 1, 2015
Grant Date -
Apr 17, 2014
app pub date -
Dec 13, 2013
filing date -
May 13, 2004
priority date (Note) -
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Abstract
The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
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