Hierarchal test block test pattern reduction in on-product test compression system
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United States of America Patent
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Sep 15, 2015
Grant Date -
Sep 10, 2015
app pub date -
May 21, 2014
filing date -
Mar 4, 2014
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Abstract
A method of creating a scan pattern test file for testing hierarchal test blocks (HTBs) of scan channels on a semiconductor chip is described. The method includes determining a maximum number of channel mask enable encodes on the semiconductor chip. A maximum number of channel mask enable encodes used for the first HTB and the second HTB are determined. A plurality of test patterns used to test the first and the second HTB into one or more mask sets dependent on the number of masks each test pattern needs are sorted. The test patterns of the mask sets of the first and second HTB to be performed in a same test pattern are combined. The number of masks per scan cycle of the combined mask sets is no more than the maximum number of channel mask enable encodes on the semiconductor chip and there is no scan slice overlap.
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