Time keeping in unknown and unstable clock architecture
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United States of America Patent
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Sep 15, 2015
Grant Date -
Oct 3, 2013
app pub date -
Mar 30, 2012
filing date -
Mar 30, 2012
priority date (Note) -
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Abstract
The present invention may provide a system with a fixed clock to provide a fixed clock signal, and a variable clock to provide a variable clock signal. The system may also include a chipset with a chipset time stamp counter (TSC) based on the fixed clock signal. A processor may include a fast counter that may be based on the variable clock signal and generate a fast count value. A slow counter may download a time stamp value based on the chipset TSC at wakeup. The slow counter may be based on the fixed clock signal and may generate a slow count value. A central TSC may combine the fast count and slow count value to generate a central TSC value.
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