Method to enable controlled side chip interconnection for 3D integrated packaging system

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United States of America Patent

PATENT NO 9136251
SERIAL NO

13997041

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Abstract

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Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheah, Bok Eng Bayan Lepas, MY 175 918
Kong, Jackson Chung Peng Bayan Lepas, MY 150 521
Ooi, Kooi Chi Bayan Lepas, MY 80 878
Periaman, Shanggar Penang, MY 24 791

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