Method of reducing system power with mixed cell memory array
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United States of America Patent
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Sep 29, 2015
Grant Date -
Feb 20, 2014
app pub date -
Sep 11, 2012
filing date -
Aug 17, 2012
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Abstract
A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.
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