Non-volatile semiconductor memory device capable of improving failure-relief efficiency
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United States of America Patent
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Sep 29, 2015
Grant Date -
Apr 9, 2015
app pub date -
Dec 12, 2014
filing date -
Jan 13, 2011
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Abstract
According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.
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