Chip testing with exclusive OR
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United States of America Patent
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Oct 6, 2015
Grant Date -
Mar 26, 2015
app pub date -
Dec 17, 2013
filing date -
Sep 23, 2013
priority date (Note) -
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Abstract
First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.
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