Mitigating instruction prediction latency with independently filtered presence predictors

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United States of America Patent

PATENT NO 9152424
APP PUB NO 20130339692A1
SERIAL NO

13523784

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bonanno, James J Wappingers Falls, US 85 545
Prasky, Brian R Wappingers Falls, US 154 1163
Saporito, Anthony Highland, US 155 788
Shum, Chung-Lung K Wappingers Falls, US 315 2136

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