Low latency data deserializer
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United States of America Patent
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Oct 6, 2015
Grant Date -
Jul 2, 2015
app pub date -
Dec 31, 2013
filing date -
Dec 31, 2013
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Abstract
A deserializer includes an input interface configured to receive an N-bit serialized stream at a source clock frequency; a modified-tree deserializing architecture that receives the first N−1 bits of the serialized stream from the input interface and generates N−1 parallel outputs corresponding to the first N−1 bits; and a last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface.
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