Memory array clock gating scheme
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United States of America Patent
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Oct 13, 2015
Grant Date -
Jun 20, 2013
app pub date -
Dec 20, 2011
filing date -
Dec 20, 2011
priority date (Note) -
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Abstract
Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.
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