Memory devices and their operation with different sets of logical erase blocks

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United States of America Patent

PATENT NO 9159427
APP PUB NO 20140085980A1
SERIAL NO

14094008

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Abstract

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Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria.

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Patent Owner(s)

  • ROUND ROCK RESEARCH, LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Roohparvar, Frankie F Monte Sereno, US 438 7998

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