Apparatus and method to prevent side channel power attacks in advanced encryption standard

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United States of America Patent

PATENT NO 9160523
APP PUB NO 20140321638A1
SERIAL NO

14151944

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Abstract

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Apparatus and method for obscuring round 1 power consumption of hardware implementation of the Advanced Encryption Standard (AES) algorithm. Additional hardware circuitry will provide consistent power consumption during round 1 of the AES algorithm. This prevents the opportunity to determine the AES key value during a side channel power attack.

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Patent Owner(s)

  • THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rooks, John W Rome, US 5 9
Weyna, Lisa Manlius, US 2 1

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