Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system
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United States of America Patent
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Oct 27, 2015
Grant Date -
N/A
app pub date -
Jan 5, 2015
filing date -
Apr 6, 2011
priority date (Note) -
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Abstract
A computer program product, apparatus and associated method/processing unit are provided for utilizing a memory subsystem including NAND flash physical memory and DRAM physical memory. Further included is a first buffer for receiving DDR signals and converting the DDR signals to SATA signals. The first buffer includes embedded DRAM physical memory. Also provided is a second buffer for receiving the SATA signals and converting the SATA signals to NAND flash signals. The second buffer is communicatively coupled to the first buffer via a first memory bus associated with a SATA protocol, the NAND flash physical memory via a second memory bus associated with a NAND flash protocol, and the DRAM physical memory.
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