Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines
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United States of America Patent
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Oct 27, 2015
Grant Date -
Nov 21, 2013
app pub date -
May 3, 2013
filing date -
May 15, 2012
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Abstract
A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.
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