Smart bridge for memory core
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United States of America Patent
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Nov 3, 2015
Grant Date -
Aug 7, 2014
app pub date -
Apr 7, 2014
filing date -
Jun 30, 2011
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Abstract
An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.
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