Dual rail single-ended read data paths for static random access memories
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United States of America Patent
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Nov 3, 2015
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N/A
app pub date -
Apr 23, 2014
filing date -
Apr 9, 2014
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Abstract
Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line translates data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device while bypassing a level shifter in the read data path.
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