Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning

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United States of America Patent

PATENT NO 9178502
SERIAL NO

14142452

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Abstract

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A delay line has at least four delay stages coupled together in a series, two multiplexers, and a phase interpolator. The first multiplexer has a first input coupled to an output of the first delay stage, and a second input coupled to an output of the third delay stage. Similarly, the second multiplexer has a first input coupled to an output of the second delay stage, and a second input coupled to an output of the fourth delay stage. The phase interpolator is coupled to outputs of the first and second multiplexers, and has an output.

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Patent Owner(s)

Patent OwnerAddress
TAHOE RESEARCH LTDDUBLIN 15 D15 YH6H

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Denler, Nicholas J Beaverton, US 3 64
Desai, Jayen J Wellington, US 10 76
Francom, Erin D Fort Collins, US 2 23
Peters, Matthew R Fort Collins, US 4 238

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