Multi-threaded processor instruction balancing through instruction uncertainty

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United States of America Patent

PATENT NO 9182991
APP PUB NO 20130205118A1
SERIAL NO

13366999

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Abstract

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A computer system for instruction execution includes a processor having a pipeline. The system is configured to perform a method including fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions, for each of the plurality of branch instructions, assigning a branch uncertainty to each of the plurality of branch instructions, for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches and balancing the instructions, based on a current summation of instruction uncertainty, in the pipeline.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Buyuktosunoglu, Alper White Plains, US 203 1349
Prasky, Brian R Wappingers Falls, US 154 1163
Srinivasan, Vijayalakshmi New York, US 100 1216

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