Data caching in a network communications processor architecture

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United States of America Patent

PATENT NO 9183145
APP PUB NO 20110289279A1
SERIAL NO

13192104

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Abstract

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Described embodiments provide a method of coherently storing data in a network processor having a plurality of processing modules and a shared memory. A control processor sends an atomic update request to a configuration controller. The atomic update request corresponds to data stored in the shared memory, the data also stored in a local pipeline cache corresponding to a client processing module. The configuration controller sends the atomic update request to the client processing modules. Each client processing module determines presence of an active access operation of a cache line in the local cache corresponding to the data of the atomic update request. If the active access operation of the cache line is absent, the client processing module writes the cache line from the local cache to shared memory, clears a valid indicator corresponding to the cache line and updates the data corresponding to the atomic update request.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brown, David A Austin, US 228 5105
Peet,, Jr Charles Edward Austin, US 4 93
Sonnier, David P Austin, US 58 1725

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